The inventive concepts described herein are related to a semiconductor memory device, and more particularly, to a semiconductor memory device that has high power integrity due to inclusion of power planes corresponding to a plurality of layers.
Semiconductor memory devices can be highly integrated by forming a plurality of layers in a non-volatile memory device. However, in such semiconductor memory devices, the occurrence of unstable power supply to a plurality of the layers, power noise coupling, electromagnetic interference (EMI), and poor heat sink capabilities are concerns.